The present invention relates to a high level synthesis method and apparatus for automatically synthesizing a register transfer level (RTL) circuit description from circuit specifications in behavioral description.
With the recent trend toward a larger scale and a shorter product cycle of LSI circuits, improvement in productivity of LSI design has become highly important. The high level synthesis technology, realizing automatic synthesis of a register transfer level (RTL) circuit description from circuit specifications in behavioral description, is known as an effective means for improving the productivity of LSI design.
For mobile equipment such as cellular phones, of which market is expected to expand further increasingly in the future, power consumption of LSI is a critical factor and should be considered in the high level synthesis technology. In the high level synthesis technology, lower power consumption has been attained by providing a smaller number of registers to implement a RTL circuit. For example, reduction of the number of registers by sharing registers is proposed in Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin, “High-Level Synthesis: Introduction to Chip and System Design”, Kluwer Academic Publishers, 1992, Japanese Patent Gazette No. 3150122 and the like.
There is a report that by adjusting the clock timings for respective registers (propagation delays from a clock source to respective registers) (semi-synchronous design), the clock frequency can be improved by 10% to 20% compared with zero-skew design (all registers have the same clock timing) (A. Takahashi, Y. Kajita, “Performance and Reliability Driven Clock Scheduling of Sequential Logic Circuits”, Proc. Asia and South Pacific Design Automation Conference, pp. 37–42, 1997).
However, the conventional high level synthesis technology has a precondition that all registers have the same clock timing (zero-skew design). Therefore, the minimum number of pipelines required to satisfy a necessary clock frequency is three, for example, in the zero-skew design although it may be reduced to two if the semi-synchronous design is adopted.
There is proposed a technique of adjusting clock timings during register repositioning (retiming) as one function of the high level synthesis technology (Xun Liu, Marois C. Papaefthymiou, Edy G. Friedman, “Maximizing Performance by Retiming and Clock Skew Scheduling”, Proc. Design Automation Conf, 1999). However, this technique, not aiming at reducing power consumption, fails to attain lower power consumption.